The present invention relates to a built-in self test circuit.
In recent years, it is considerably important to perform a test having a high fault detection capacity so as to assure the quality of LSIs. It is, however, more difficult to test the internal arrangement of an LSI from the limited external pins due to the recent development of larger scale LSIs. In addition, the test contents are also complicated. A test circuit itself is assumed to be built into an LSI in design for testability (DFT). Typical techniques are a built-in self test (BIST) technique and a scan technique. The present invention relates to the BIST technique.
In this BIST technique, a built-in self test is known wherein a test function is built into a semiconductor chip to perform a test. Built-in self test arrangements are classified into a centralized arrangement in which one pattern generator and one pattern compressor are shared by all functional blocks and a distributed arrangement in which a pattern generator and a pattern compressor are arranged for each functional block.
With this arrangement, the number of parts of each constituent component or the wiring amount between the respective constituent components greatly influence the hardware amount or space factor in the LSI.
For example, a pseudorandom pattern generator is generally used as a pattern generator. Typical examples of the pseudorandom pattern generator are a linear feedback shift register and a weighted linear shift register. In use of a linear feedback shift register having a bit width corresponding to the number of inputs of circuits under test (CUT), a pseudorandom pattern is generated by the linear feedback shift register, and the output from the linear feedback shift register is input to the circuits under test.
In the method using the linear feedback shift register or weighted linear feedback shift register as the test pattern generator, however, the linear feedback shift register having the bit width corresponding to the number of inputs of the circuits under test must be used, and a large amount of hardware is required for a multiple input circuit.
In addition, a large number of patterns and a long test execution time are required to obtain a high fault coverage in a linear feedback shift register. A long fault simulation time is undesirably required to evaluate the patterns accordingly.
The weighted linear feedback shift register has an advantage in that the number of patterns is reduced because convergence of the fault coverage is improved. However, weighting hardware such as OR and AND gates is additionally required, resulting in inconvenience.
When a pattern compressor is taken into consideration, two linear feedback shift registers (LFSRs) or multiple input linear feedback shift registers (MISRs) are used as the first and second compressors in the pattern compressor arrangement. In the first compressors, as shown in FIG. 10, pattern generators (LFSRs) 1.sub.1 to 1.sub.4 supply M test patterns to four functional blocks 2.sub.1 to 2.sub.4 as circuits under test, and data of N bits.times.M patterns output from the functional blocks 2.sub.1 to 2.sub.4 are spatially compressed into data of 1 bit.times.M patterns by space compressors 3.sub.1 to 3.sub.4 using the multiple input linear feedback shift registers (MISRs) embedded in the functional blocks (i.e., the functional blocks and the pattern compressors are arranged adjacent to each other in the chip layout, and the wiring length between them is short).
In the second compressors, all data each consisting of 1 bit.times.M patterns obtained by compressing the data from the functional blocks 2.sub.1 to 2.sub.4 by the space compressors 3.sub.1 to 3.sub.4 are respectively collected by compression lines 4.sub.1 to 4.sub.4, and time compressors 5.sub.1 to 5.sub.4 using the linear feedback shift registers (LFSRs) separate from the four functional blocks (the compressors are arranged separate from the functional blocks in the chip layout, and the wiring length between them is long) compress all the data into data each consisting of one pattern. The resultant values are compared with a given expected value prestored in the chip (Reference: P. P. Glelsinger: Design and test for the 80386, IEEE Design & Test of Comp., 4, 3, pp. 42-50 (1987)).
Since the multiple input linear feedback shift registers are used as the space compressors 3 (3.sub.1 to 3.sub.4) as the first compressors for the functional blocks, and four separate linear feedback shift registers are used as time compressors 5 (5.sub.1 to 5.sub.4) serving as the second compressors, the amount of hardware constituting the pattern compressor is undesirably large.
As an arrangement of the space compressor having a smaller amount of hardware than that of the compressor using the multiple input feedback shift registers, a compressor using exclusive OR gates is known (Reference: S. M. Reddy et al.: A data compression technique for built-in self-test, IEEE Trans. Comp., Col. 37, No. 9, pp. 1151-1156 (Sep. 1988)).
The degree of space compression (compressible bit width) free from missed faults depends on a functional block under test in the compressor using only the exclusive OR gates. This arrangement is suitable for a pattern compressor in which space and time compressors are located adjacent to each other to perform a centralized self test. However, when this arrangement is used as a distributed self test pattern compressor, a wiring amount between the space and time compressors is undesirably increased in the presence of a compressor having a low degree of space compression in the functional block under test.